Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural Computation Using Stochastic LogicONOMI, Takeshi; KONDO, Taizo; NAKAJIMA, Koji et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 626-629, issn 1051-8223, 4 p., 1Conference Paper

Analysis and simulation of a mixed-mode neuron architecture for sensor conditioningZATORRE-NAVARRO, Guillermo; MEDRANO-MARQUES, Nicolas; CELMA-PUEYO, Santiago et al.IEEE transactions on neural networks. 2006, Vol 17, Num 5, pp 1332-1335, issn 1045-9227, 4 p.Article

A survey of software and hardware use in artificial neural networks : NEW APPLICATIONS OF ARTIFICIAL NEURAL NETWORKS IN MODELING & CONTROLBAPTISTA, Darío; ABREU, Sandy; FREITAS, Filipe et al.Neural computing & applications (Print). 2013, Vol 23, Num 3-4, pp 591-599, issn 0941-0643, 9 p.Article

Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational SystemsRAJENDRAN, Bipin; YONG LIU; SEO, Jae-Sun et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 1, pp 246-253, issn 0018-9383, 8 p.Article

Real-time neural network inversion on the SRC-6e reconfigurable computerDUREN, Russell W; MARKS, Robert J; REYNOLDS, Paul D et al.IEEE transactions on neural networks. 2007, Vol 18, Num 3, pp 889-901, issn 1045-9227, 13 p.Article

Experimental demonstration of associative memory with memristive neural networksPERSHIN, Yuriy V; DI VENTRA, Massimiliano.Neural networks. 2010, Vol 23, Num 7, pp 881-886, issn 0893-6080, 6 p.Article

Large Developing Receptive Fields Using a Distributed and Locally Reprogrammable Address―Event ReceiverBAMFORD, Simeon A; MURRAY, Alan F; WILLSHAW, David J et al.IEEE transactions on neural networks. 2010, Vol 21, Num 2, pp 286-304, issn 1045-9227, 19 p.Article

High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann MachinesLE LY, Daniel; CHOW, Paul.IEEE transactions on neural networks. 2010, Vol 21, Num 11, pp 1780-1792, issn 1045-9227, 13 p.Article

Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural SimulationsBENJAMIN, Ben Varkey; GAO, Peiran; MCQUINN, Emmett et al.Proceedings of the IEEE. 2014, Vol 102, Num 5, pp 699-716, issn 0018-9219, 18 p.Article

Silicon-Based Dynamic Synapse With Depressing ResponseDOWRICK, Thomas; HALL, Steve; MCDAID, Liam J et al.IEEE transactions on neural networks and learning systems (Print). 2012, Vol 23, Num 10, pp 1513-1525, issn 2162-237X, 13 p.Article

The SpiNNaker ProjectFURBER, Steve B; GALLUPPI, Francesco; TEMPLE, Steve et al.Proceedings of the IEEE. 2014, Vol 102, Num 5, pp 652-665, issn 0018-9219, 14 p.Article

A 128 x 128 120 dB 15 μs Latency Asynchronous Temporal Contrast Vision SensorLICHTSTEINER, Patrick; POSCH, Christoph; DELBRUCK, Tobi et al.IEEE journal of solid-state circuits. 2008, Vol 43, Num 2, pp 566-576, issn 0018-9200, 11 p.Article

Real-time computing platform for spiking neurons (RT-spike)ROS, Eduardo; ORTIGOSA, Eva M; AGIS, Rodrigo et al.IEEE transactions on neural networks. 2006, Vol 17, Num 4, pp 1050-1063, issn 1045-9227, 14 p.Article

A simple programmable axonal delay scheme for spiking neural networksDOWRICK, Thomas; HALL, Steve; MCDAID, Liam et al.Neurocomputing (Amsterdam). 2013, Vol 108, pp 79-83, issn 0925-2312, 5 p.Article

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithmNAMBIAR, Vishnu P; KHALIL-HANI, Mohamed; MARSONO, M. N et al.Neurocomputing (Amsterdam). 2014, Vol 145, pp 285-302, issn 0925-2312, 18 p.Article

An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision SensorsCAMUNAS-MESA, Luis; ZAMARREFIO-RAMOS, Carlos; LINARES-BARRANCO, Alejandro et al.IEEE journal of solid-state circuits. 2012, Vol 47, Num 2, pp 504-517, issn 0018-9200, 14 p.Article